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 IRFB16N50K, SIHFB16N50K
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 89 27 43 Single
D
FEATURES
500 0.285
* Low Gate Charge Qg Results in Simple Drive Requirement Ruggedness
Available
RoHS* * Improved Gate, Avalanche and Dynamic dV/dt COMPLIANT
* Fully Characterized Capacitance and Avalanche Voltage and Current * Low RDS(on) * Lead (Pb)-free Available
TO-220
G
APPLICATIONS
* Switch Mode Power Supply (SMPS) * Uninterruptible Power Supply
S G D S N-Channel MOSFET
* High Speed Power Switching * Hard Switched and High Frequency Circuits
ORDERING INFORMATION
Package Lead (Pb)-free SnPb TO-220 IRFB16N50KPbF SIHFB16N50K-E3 IRFB16N50K SIHFB16N50K
ABSOLUTE MAXIMUM RATINGS TC = 25 C, unless otherwise noted
PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque VGS at 10 V TC = 25 C TC = 100 C SYMBOL VDS VGS ID IDM EAS IAR EAR PD dV/dt TJ, Tstg LIMIT 500 30 17 11 68 2.3 310 17 28 280 11 - 55 to + 150 300d 10 1.1 UNIT V
A W/C mJ A mJ W V/ns C lbf * in N*m
TC = 25 C
for 10 s 6-32 or M3 screw
Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. Starting TJ = 25 C, L = 2.2 mH, RG = 25 , IAS = 17 A. c. ISD 17 A, dI/dt 500 A/s, VDD VDS, TJ 150 C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91096 S-80567-Rev. A, 20-Jun-08 www.vishay.com 1
WORK-IN-PROGRESS
IRFB16N50K, SIHFB16N50K
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 0.50 MAX. 62 0.44 C/W UNIT
SPECIFICATIONS TJ = 25 C, unless otherwise noted
PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode
D
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs
VGS = 0 V, ID = 250 A Reference to 25 C, ID = 1 mA VDS = VGS, ID = 250 A VGS = 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 125 C VGS = 10 V ID = 10 Ab VDS = 50 V, ID = 10 A
500 3.0 5.7
0.58 0.285 -
5.0 100 50 250 0.350 -
V V/C V nA A S
Ciss Coss Crss Coss Coss eff. Qg Qgs Qgd td(on) tr td(off) tf VGS = 10 V
VGS = 0 V, VDS = 25 V, f = 1.0 MHz VDS = 1.0 V, f = 1.0 MHz VGS = 0 V VDS = 400 V, f = 1.0 MHz VDS = 0 V to 400 Vc ID = 17 A, VDS = 400 Vb
-
2210 240 26 2620 63 120 60 18 28 20 77 38 30
89 27 43 ns nC pF
VDD = 250 V, ID = 17 A, RG = 8.8 , VGS = 10 Vb
-
-
490 5710
17 A 68 1.5 730 8560 V ns nC
G
S
TJ = 25 C, IS = 17 A, VGS = 0 Vb TJ = 25 C, IF = 17 A, dI/dt = 100 A/sb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 s; duty cycle 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
www.vishay.com 2
Document Number: 91096 S-80567-Rev. A, 20-Jun-08
IRFB16N50K, SIHFB16N50K
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted
100
TOP
100
VGS 15V 10V 8.0V 7.5V 7.0V 6.5V 6.0V 5.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current ( )
T J = 150C
10
BOTTOM
10
1
5.5V
T J = 25C VDS = 100V 60s PULSE WIDTH 1.0 4 5 6 7 8 9 10 11 12 13 14 15 16
0.1 0.1 1
60s PULSE WIDTH Tj = 25C 10 100
V DS, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics
100
RDS(on) , Drain-to-Source On Resistance (Normalized)
TOP VGS 15V 10V 8.0V 7.5V 7.0V 6.5V 6.0V 5.5V
3.0
ID, Drain-to-Source Current (A)
2.5
ID = 17A VGS = 10V
10
BOTTOM
2.0
5.5V
1.5
1
1.0
0.5
60s PULSE WIDTH Tj = 150C 0.1 0.1 1 10 100 V DS, Drain-to-Source Voltage (V)
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
T J , Junction Temperature (C)
Fig. 2 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91096 S-80567-Rev. A, 20-Jun-08
www.vishay.com 3
IRFB16N50K, SIHFB16N50K
Vishay Siliconix
100000
VGS = 0V, f = 1 MHZ Ciss = C gs + C gd, C ds SHORTED Crss = C gd Coss = C ds + C gd
100.00
10000
ISD, Reverse Drain Current (A)
C, Capacitance(pF)
Ciss
1000
T J = 150C 10.00
Coss
100
T J = 25C 1.00
Crss
10
VGS = 0V
1 1 10 100 1000
0.10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD, Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
12.0 ID= 17A
VGS, Gate-to-Source Voltage (V)
1000 VDS= 400V VDS= 250V VDS= 100V OPERATION IN THIS AREA LIMITED BY R DS(on)
8.0
ID, Drain-to-Source Current (A)
10.0
100
6.0
10
100sec 1msec
4.0
1 Tc = 25C Tj = 150C Single Pulse 0.1 1 10 100 10msec 1000 10000
2.0
0.0 0 10 20 30 40 50 60 QG Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
VDS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area
www.vishay.com 4
Document Number: 91096 S-80567-Rev. A, 20-Jun-08
IRFB16N50K, SIHFB16N50K
Vishay Siliconix
RD VDS VGS D.U.T. + - VDD 10 V
20
15
ID, Drain Current (A)
RG
10
Pulse width 1 s Duty factor 0.1 %
Fig. 10a - Switching Time Test Circuit
5
VDS 90 %
0 25 50 75 100 125 150 T C , Case Temperature (C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
10 % VGS td(on) tr td(off) tf
Fig. 10b - Switching Time Waveforms
1
Thermal Response ( Z thJC )
D = 0.50
0.1
0.20 0.10 0.05
0.01
0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.001 0.01 0.1 1
0.001 1E-006 1E-005 0.0001
t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
Driver
RG
20 V
D.U.T.
IAS tp
+ - VDD
A
IAS
0.01
Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91096 S-80567-Rev. A, 20-Jun-08
Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5
IRFB16N50K, SIHFB16N50K
Vishay Siliconix
600
EAS , Single Pulse Avalanche Energy (mJ)
500
ID 7.6A 11A BOTTOM 17A TOP
400
300
200
100
0 25 50 75 100 125 150
Starting T J , Junction Temperature (C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator Same type as D.U.T.
50 k
12 V
VGS QGS
QG
0.2 F
0.3 F
QGD D.U.T.
+ -
VDS
VG
VGS
3 mA
Charge
IG ID Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
www.vishay.com 6
Document Number: 91096 S-80567-Rev. A, 20-Jun-08
IRFB16N50K, SIHFB16N50K
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations * Low stray inductance * Ground plane * Low leakage inductance current transformer
+ +
-
RG
* * * *
dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test
+ VDD
Driver gate drive P.W. Period D=
P.W. Period VGS = 10 V*
D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt
VDD
Re-applied voltage Inductor current
Body diode forward drop
Ripple 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91096.
Document Number: 91096 S-80567-Rev. A, 20-Jun-08
www.vishay.com 7
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000 Revision: 18-Jul-08
www.vishay.com 1


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